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The goal of this work is to investigate ways of providing SEU mitigation for FPGA-based DSP and digital communications systems at a lower cost than TMR.

We have hypothesized that many SEUs that affect these types of systems may manifest effects similar to noise that the systems are already designed to handle. Our initial investigations this year have focused on the digital filter in a simple digital communications receiver. Fault injection experments have shown that the vast majority of SEUs did not cause a significant increase in the bit error rate (BER) at the output of the receiver during a practical test.

With this in mind, a low-cost mitigation technique could be used which focuses only on the SEUs that cause significant degradation in BER. One of these reduced-cost techniques we plan on investigating is reduced-precision redundancy (RPR). This technique involves the triplication of only the most significant bits of the computation modules. The more bits that are replicated, the more error handling is provided. We will be investigating this technique mathematically in terms of a digital communications system as well as in further fault injection experiments.