FPGAs in Space
Field-programmable gate arrays (FPGAs) are an increasingly attractive solution for space systems. They perform well in high-throughput signal processing applications often used in space. Furthermore, their programmability allows in-field application adjustments. This is an ideal attribute for a space-based system as the same device can be used for multiple applications at different times, saving space and weight.
Unfortunately, FPGAs are susceptible to radiation-induced single-event upsets (SEU). Since FPGAs store their programming data, or configuration in an SRAM-like configuration memory, an SEU can actually alter the intended circuit. As such, SRAM-based FPGAs destined for a radiation environment must employ a form of SEU mitigation to insure reliable operation.
SRAM-based FPGAs are sensitive to radiation effects causing single-event upsets (SEUs). These upsets may effect many parts of the FPGA including configuration memory, flip-flops, and other programmable resources. The configuration memory represents the vast majority of the susceptible bits and is thus of the most interest for SEU mitigation.
Due to the programmable nature of FPGAs, their susceptibility to SEUs depends on the set of configurable logic utilized for a particular application. This is called the operational, or dynamic, sensitivity. The sensitivity of a particular design can be accurately characterized by fault-injection tools and radiation testing. Extensive tests have characterized the dynamic sensitivity of a variety of FPGA applications.
FPGAs have a set static cross section that can be measured and characterized. Each user design that is loaded into the FPGA configuration memory has a distinct dynamic cross section that is smaller than the static cross section. This dynamic cross section can be characterized by fault-injection tools and radiation testing.
I worked in researching ways to counteract these problems by inserting redundancy into the FPGA design to be used in these types of systems. The redundancy allows the chip to recover from upsets in the configuration memory, masking any errors caused. Continue on to my SEU Mitigation page to learn more about protecting the FPGA design from these upsets.