Partial TMR
SEU sensitivity in the configuration memory can be mitigated through techniques such as Triple Modular Redundancy (TMR). These mitigation strategies offer tremendous improvements in reliability, but are often expensive in terms of FPGA resource utilization, power consumption, etc.. We seek new ways to offer acceptable levels of reliability at much lower costs.One way to reduce the cost of mitigation is to apply mitigation selectively on a subset of an FPGA design. By selectively applying design mitigation, the designer can trade off the improvements in reliability with the cost of design mitigation. In this paper we will show how applying TMR to a subset of the user design allows the designer to most effectively make this trade-off. Applying TMR selectively to a user design is called ``Partial TMR''. We at BYU have developed a software tool that can apply Partial TMR automatically to an FPGA design.
For more information, you can read a paper I wrote and presented at the International Reliability Physics Symposium in 2006: Improving FPGA Design Robustness With Partial TMR. Or if you don't have access to IEEE papers, there is an older version I presented at the Military Applications for Programmable Logic Devices conference in 2005: http://www.klabs.org/mapld05/program_sessions/session_e.html
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