Brian Pratt's Homepage

• 1: Welcome
  • 1.1: About Me
• 2: Projects
  • 2.1: Software
    • 2.1.1: Web Cloner
    • 2.1.2: Chess
    • 2.1.3: RCS
  • 2.2: RTOS
  • 2.3: Senior Project
  • 2.4: LANL Internship
  • 2.5: DES Cracker
  • 2.6: Digital Comm
• 3: Research
  • 3.1: FPGAs in Space
  • 3.2: SEU Mitigation
  • 3.3: Partial TMR
  • 3.4: Digital Comm
• 4: Docs
  • 4.1: Linux
  • 4.2: Mac OS X
  • 4.3: Other
• 5: Software
  • 5.1: Geolocator.app
  • 5.2: Awesome Ball
  • 5.3: AccSim
  • 5.4: Roomote
• 6: Resume
• 7: Contact

Research

From 2004-2010, I worked as a research assistant to Dr. Michael Wirthlin in the BYU Configurable Computing Lab (a.k.a. FPGA Lab). My general area of research was in FPGA reliability--the effects of radiation on Field Programmable Gate Arrays.

In the past, I worked on improving a tool developed at BYU to perform SEU Mitigation on EDIF design files. The tool uses Triple Modular Redundancy to protect the user design from Single-Event Upsets. I used this tool to perform partial mitigation of the design with the hopes of acheiving the desired level of reliability with a minimal cost. The tool is now very sophisticated and is available as part of the BYU EDIF tools, an open source tool suite available on sourceforge.net.

For my PhD research, I studied the effects of radiation on digital communications systems on FPGAs. Communications systems have specific properties that can be exploited to make reduced-cost reliability techniques (compared to the expensive, but very effective TMR). I have presented some aspects of this work at MAPLD 2008 and at FPL 2009 and other forums. My dissertation is entitled Analysis and Mitigation of SEU-induced Noise on FPGA-based DSP Systems.