From 2004-2010, I worked as a research assistant to Dr. Michael Wirthlin in the BYU Configurable Computing Lab (a.k.a. FPGA Lab). My general area of research was in FPGA reliability--the effects of radiation on Field Programmable Gate Arrays.
In the past, I worked on improving a tool developed at BYU to perform SEU Mitigation on EDIF design files. The tool uses Triple Modular Redundancy to protect the user design from Single-Event Upsets. I used this tool to perform partial mitigation of the design with the hopes of acheiving the desired level of reliability with a minimal cost. The tool is now very sophisticated and is available as part of the BYU EDIF tools, an open source tool suite available on sourceforge.net.
For my PhD research, I studied the effects of radiation on digital communications systems on FPGAs. Communications systems have specific properties that can be exploited to make reduced-cost reliability techniques (compared to the expensive, but very effective TMR). I have presented some aspects of this work at MAPLD 2008 and at FPL 2009 and other forums. My dissertation is entitled Analysis and Mitigation of SEU-induced Noise on FPGA-based DSP Systems.